The present invention relates to a semiconductor memory device comprising two spaced, electrically conductive contact layers and a layer comprising amorphous silicon material extending between the contact layers, and methods of producing such. The invention relates also to memory matrix array devices using such memory devices.
A semiconductor memory device of the above kind is described in PCT WO 90/13921. This device comprises a thin layer of amorphous silicon material on one side of which is provided a first conducting layer, such as chromium, and on the other side of which a second conducting layer of a selected metal, such as vanadium, is deposited. The amorphous silicon layer may be hydrogenated n type, doped with phosphorous, or hydrogenated p type, doped with boron, having a thickness in the range 20 to 350 nm and is preferably doped to have a conductivity in the bulk state of at least 10.sup.-6 (ohms cm).sup.-1. In order for the device to perform a memory function, its electrical characteristics are altered by a so-called forming process which involves applying a voltage, or series of voltages, across the device which convert its structure to one having analogue memory properties. This forming process has the effect of reducing the device resistance, from around 10.sup.9 ohms prior to this process by, for example, around two orders of magnitude. After this forming, the device can be set and reset to a resistance which is a measure of an applied voltage, the resistance value being retained after removal of the applied voltage thereby providing a programmed device. The device differs in this respect from devices which only retain a given state while maintained by a holding voltage and from known binary memory devices which effectively store just two values in response to two respective ranges of voltages.
An explanation of the change in the structure and behaviour resulting from such a forming process, given in the paper entitled "Metal-semiconductor transition in electroformed chromium/amorphous silicon/vanadium thin-film structures" by J. Hajto et al in Philosophical Magazine B. 1994, Vol. 69, No. 2, pages 237-251, is that the forming process creates a localised filamentary region which is highly conducting. It is suggested in this paper that the filamentary region, which can be less than 0.5 micrometers in diameter, is likely to be caused by the top metal diffusing into the doped amorphous silicon layer during the forming process which produces a region of mixed metal and silicon of some form. Experiments reported in that paper involved Cr/p.sup.+ a-Si:H/V sandwich structures having an active area of 10 micrometers in diameter and with the amorphous silicon layer being 0.01 micrometers in thickness. The structures initially have a low voltage resistance of around 10.sup.9 ohms, due, it is said, to metal-semiconductor Schottky barriers at the contacts, which is lowered to around 10.sup.3 ohms by a forming process that involves applying a sequence of single 300 ns voltage pulses of increasing magnitude to around 14V with the top, vanadium, contact being of positive polarity. Following this forming, the structure exhibits fast analogue memory switching by demonstrating non-volatile resistance states between Ron equal to 10.sup.3 ohms and Roff equal to 10.sup.6 ohms under the influence of a single voltage pulse of 100 ns duration and of magnitudes between 2 and 6v. Similar results are described in the aforementioned PCT WO 90/13921. In one described example using the formed device as a memory element, a positive, WRITE, pulse of 3.4V and 100 ns duration is applied to the chromium contact resulting in an ON state of 2.times.10.sup.3 ohms and an opposite polarity, ERASE, pulse is applied at successively higher voltages through which it was found that at a certain threshold voltage the device resistance gradually increases with each successively higher applied voltage until at around 3.0 V a final resistance state of approximately 4.times.10.sup.5 ohms is achieved. All these states were non-volatile and stable with the device retaining the conductivity state to which it had last been set. Between the upper and lower switching thresholds the device resistance is primarily a function of applied voltage pulse. According to experimental results given in the paper by Hajto et al, the I-V characteristics of the device for different analogue memory states are generally symmetrical and linear. The analogue memory semiconductor devices are suitable for use, for example, as non-volatile, and reprogrammable, memory elements in analogue neural networks.
In PCT WO 90/00817 there is described an electrical switching device which comprises an amorphous silicon compound layer formed by reacting amorphous silicon or an amorphous silicon compound such as amorphous silicon carbide, oxide or nitride, with a passivating agent such as hydrogen, and two conducting electrodes on the amorphous silicon compound layer. The device initially has a relatively high resistance and is similarly subjected to a forming operation by applying a high voltage which is said to cause a disc like area of crystalline elemental silicon to be formed together with the loss of the overlying part of an electrode, thus creating a localised filament through the device. Once formed in this way, the device exhibits a voltage controlled negative resistance whereby it has a low resistance until it is subjected to a high voltage or current whereupon it has a high resistance. The change in resistance effect is explained as being due to ohmic heating in the filamentary region and the thermionic and/or field effect emission of electrons from that region into regions having lower electron mobilities.